Media applications have been driving microprocessor development for more than one decade. In fact, most computing upgrades in recent years have been driven by the Internet or media applications predominantly within consumer segments, but also in enterprise segments for entertainment, speech recognition, as well as multitasking environments. Nevertheless, future media applications will demand even higher computational requirements from future microprocessors. As a result, tomorrow's personal computer (PC) will be richer in audio/visual effects as well as improved usability, while enabling computing to merge with communications.
Accordingly, Internet audio and video streaming, as well as image processing and video content creation are continuously driving system architects to design even faster microprocessors. In order to improve microprocessor performance, several techniques have been utilized to improve the efficiency of modern day processors. One such technique for providing more efficient microprocessors is utilizing “Dynamic Execution”. In summary, Dynamic Execution functions by determining the most efficient manner for executing program instructions, irrespective of the order in which the program instructions are received.
Dynamic Execution utilizes front end logic that fetches the next instructions within a program and prepares the instructions for subsequent execution in the machine pipeline. This front end logic utilizes highly accurate branch prediction logic that uses the past history of program execution to speculate where the program is going to execute next. The predicted instruction address from this front end branch prediction logic is used to fetch instruction bytes from a level two (L2) cache. Once fetched, these instruction bytes are decoded into basic operations called uOPs (micro-operations) that the execution core can execute.
As such, these micro-operations are provided to a Dynamic Execution unit, along with a sequence number assigned to each micro-operation. The Dynamic Execution logic has several buffers that it uses to sort and reorder the flow of instructions to optimize performance as instructions go down the pipeline and get scheduled for execution. This Dynamic Execution allows program instructions to proceed around the delayed instructions as long as they do not depend on those delayed instructions. As a result, micro-operation do not stall when following delayed instructions, in which case, efficiency dictates that the instructions execute in an out-of-order fashion.
The Dynamic Execution logic generally includes retirement logic that reorders the instructions executed in an out-of-order fashion (dynamic manner) back into the original program order. As a result, out-of-order execution generates a pool of active micro-operations that can be executed in a manner which is more efficient than conventional systems. However, in order to implement out-of-order execution, register renaming logic is required to rename logical registers in order to utilize 144-entry physical register files. In addition, the renaming logic is required for execution of legacy instructions with improved efficiency.
Unfortunately, segment registers associated with floating point instructions are generally renamed once provided to a renaming unit. Consequently, when a memory accessing floating point micro-instruction is generated, a source segment of the micro-operation is renamed. However, under certain conditions, software access to the renamed source segment information is vital in order to resolve events which may be triggered by the floating point micro-instruction. Unfortunately, current mechanisms for saving the original source of the memory referencing micro-instruction are unduly complicated. Therefore, there remains a need to overcome one or more of the limitations in the above-described, existing art.